Design a synchronous sequential circuit to check the highest number of ones and zeros in the last 3 input samples. Your ckt should give 1 at the O/P if the last 3 samples at the input has more 1's similarly 0 when the no. of zeros is high.
Eg:
IN : 001110110000
OUT: 0111111000
Constraints:
1) You are supposed to use only Multiplexers and DFFs for
your design. No external gates. To be specific, 1 4:1 Mux only.
2) Design should be optimized one.
3) Only one clock is available to you. And it is given that the
input is sampled at that clock rate only.
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